The AU-G0100 Interrupt Controller AMBA APB Core provides an interrupt controller peripheral
for AMBA based SOCs. It aggregates 32 interrupt requests into 8 interrupt outputs. It connects
seamlessly to the AMBA APB Bus as an AMBA Bus slave. The Interrupt Controller AMBA
APB Core is available as a synthesizable Verilog model from Aurora VLSI, Inc.

• 32 interrupt requests
- independently enabled
- level or edge sensitive (configurable)
- active high or low (configurable)
- deglitched
• 8 interrupt outputs (configurable)
• Each interrupt request is assigned to one or more interrupt outputs that it will trigger
• 32 interrupt request priority levels
• Each interrupt request is assigned a priority level
• Priority level of highest priority interrupt request for each interrupt output is available
for vectored interrupt handling
• Pending registers show all pending interrupt requests
• Service registers show highest priority pending requests
• Software interrupt set and clear