The Multilayer AMBA Bus Interconnect provides a configurable multilayer AMBA AHB Bus
interconnect. It can be configured as a two to sixteen layer AMBA AHB Bus interconnect. Up to
63 AMBA AHB Bus masters and 63 AMBA AHB Bus slaves can be supported. The read and
write data widths are user configurable to either 32 bits or 64 bits. The Multilayer AMBA Bus
Interconnect is available as a synthesizable Verilog model from Aurora VLSI, Inc.

• 2 to 16 layer AMBA AHB bus interconnect- user configurable
• 32 bit or 64 bit data widths- user configurable
• 1 to 63 AMBA Bus masters- user configurable
• 1 to 63 AMBA Bus slaves- user configurable
• 0 to 15 AMBA Bus masters per AMBA AHB bus
• 0 to 15 AMBA Bus slaves per AMBA AHB bus
• Fully pipelined for highest throughput
• Low bus to bus latency
• Supports all required AMBA AHB bus features
• Supports all AMBA AHB bus responses- OKAY, ERROR, RETRY, SPLIT
• Unused AMBA AHB bus layers, AMBA Bus master interfaces, AMBA Bus slave
interfaces, AMBA Bus address registers, decoders, arbiters, etc. are not in the
synthesized netlist to minimize gate count.