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Aurora VLSI, Inc.:AU-B0001
类型:软IP
简短描述:AMBA AHB/APB Bus Bridge Core
详细描述:

The AMBA AHB/APB Bus Bridge is a bridge between an AMBA AHB Bus and an AMBA APB
Bus. It includes the slave select line decoder for the AMBA APB Bus. Sixteen AMBA APB Bus
slaves are supported. The AMBA AHB/APB Bus Bridge is available as a synthesizable Verilog model from Aurora VLSI, Inc.


工艺:
代工厂:
应用:
特色:

• AMBA AHB Bus to APB Bus bridge function
• AMBA APB Bus decoder function
• 16 AMBA APB Bus slaves
• Supports all AMBA AHB Bus transaction types
• Supports all AMBA AHB Bus burst types
• Supports AMBA AHB data sizes of 1, 2, and 4 bytes
• 16 slave address registers- one register per slave
- base address of the slave’s address space
- size of the slave’s address space
• Synchronous or asynchronous AMBA AHB bus clock and AMBA APB bus clock

    Aurora VLSI, Inc.:AU-B0000
    Aurora VLSI, Inc.:AU-B0002
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