The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel?UTMI standard. It provides a High/Full-Speed USB analog front-end with a build-in 8-bit/16-bit parallel interface, therefore, it is easy to interface with USB2.0 Device System. It can work as host phy or device phy, depending on different setting of DPPULLDOWN and DMPULLDOWN.

SMIC13 general 1P6M process  
Compliant with the USB Spec Rev2.0  
Compliant with the UTMI Spec Rev1.05  
Supports 480Mbit/s 揌igh Speed?and 12Mbit/s 揊ull Speed? 
Supports 60MHz/8-bit unidirectional interface and 30MHz/16-bit bidirectional interface  
12MHz external crystal, internal oscillator and PLL are used for generating high-speed internal clock and CLKOUT output  
Internal terminations include 1.5Kohm pull-up resistor switching on DP/DM in the FS mode and the HS chirp mode  
Clock and data recovery from serial stream on the USB bus  
Supports detection of USB reset, suspend, resume and remote-wake-up features  
Supports the test modes defined in the USB2.0 Specification.  
NRZI and Bit Stuff encoding and decoding  
Supports low/full speed serial mode  
Works as host phy or device phy by setting DPPULLDOWN and DMPULLDOWN