The ZSP800 extends the successful ZSP product family and introduces the company’s third generation ZSP processor architecture. The G3 architecture has been developed to meet the needs of high-performance applications, such as high-definition audio and wireless processing, and incorporates a number of innovative features to provide the right balance between silicon cost and processing.  While offering the capabilities one would expect from a high-performance DSP, the ZSP800 does not suffer in terms of clock speed and is able to achieve very high clock rates.  For a 65 nm generic process, the eight-stage ZSP800 delivers approximately 450 MHz under worst case operating conditions with standard cell libraries. The ZSP800 also integrates a number of powerful execution units and parallel compute capabilities enabling multiple operations per clock cycle.  The resulting combination of clock speed and processing provides unprecedented performance from a single-core solution, satisfying the high-end audio demands of applications such as Blu-Ray/HD-DVD players and HD DTV.

Advanced DSP architecture 
 8-stage pipeline
 4+1 instructions per cycle
 Quad-MAC, Six-ALU
 Mixed 16/32/40-bit datapath for native 32-bit precision
 72-bit multiplier accumulator
 450 MHz for worst case operating conditions in a 65 nm 
Application oriented ISA
 16/32-bit width instructions
 Extended precision MAC
 Divide Assist, Norm, Viterbi
High-performance subsystem
 Dual 64-bit load/store units 
 Innovative MSS support large TCM
 4 GW addressable space
 AHB/AXI support
 Z.TurboTM interface for integrating hardware accelerators
Backward compatible with 
ZSP G2 Architecture