The ZSP540 processor core is a high-performance/ power-efficient quad-MAC/six-ALU implementation of the G2 architecture. The ZSP540 utilizes a 16-bit architecture with extensive 32-bit capabilities and sets an unmatched balance of performance, power and memory utilization efficiency. The Z.Turbo accelerator enables the SoC designer to extend the ZSP540 Instruction Set and the ability to add application-specific acceleration logic.

VeriSilicon ZSP cores are fully synthesizable and completely technology independent. The cores have been proven in ASICs and standard products alike. The ZSP architectures have been optimized for optimal code density, energy efficiency, compiler performance and system integration.

4+1 instructions per cycle, Quad-MAC/Six-ALU DSP core  
Customizable instruction set using Z.turbo port 
Extensive 32-bit and 40-bit support 
Dual 64-bit wide Load/Store data ports 
24-bit address space both instruction and data memory  
Orthogonal, 16/32-bit load-store instruction set  
Hardware controlled pipeline protection  
Embedded trace and profiling capability 
Static, single phase clocked design 
Synthesizable, single phase clocked design  
Available with full AMBA (AHB) support  
Code compatible with all other ZSP cores