The ZSP500 Core is a four-issue processor, dual-MAC implementation of the ZSP?G2 architecture. Designed to meet the demands of media-rich, power-critical applications, such as consumer and wireless applications, the ZSP500 is the leader in its space. The Z.Turbo feature provides user-configurability and application-specific acceleration.

VeriSilicon ZSP processor cores are fully synthesizable and completely technology independent. The Cores have been proven in ASICs and standard products alike. The ZSP architectures have been optimized for optimal code density, energy efficiency, compiler performance and system integration.
 

4 instructions per cycle, Dual MAC/Five ALU DSP core 
Automatic and programmer controlled power management 
Customizable instruction set using Z.turbo port 
Extensive 32-bit and 40-bit support 
16/32-bit instruction set 
24-bit address space for both instruction and data memory 
Orthogonal, load-store instruction set 
Hardware controlled pipeline protection 
Synthesizable, single phase clocked design 
Code compatible with all other ZSP cores 
Embedded trace and profiling capability 
Available with full AMBA (AHB) support