The WSP1600 DSP core is a high-speed scalar (one instruction per clock cycle) 16-bit fixed-point Digital Signal Processor optimized for communications, consumer electronics, multi-media, and other high-speed signal processing applications. 

The WSP1600 DSP core combines the popular ADSP-218X architecture (3 Computational Units – ALU, MULT/MAC, & Shifter, a Program Sequencer, 2 Data Address Generators, 2 DMA Ports, 2 Serial Ports, a Programmable Timer, Flag I/O, General Purpose I/Os, extensive Interrupt capability, IO space registers and on-core Program Memory (PM) and Data Memories (DM)) and WinStream's own Special Feature Enhanced Mode, which includes hooks for adding new instructions and additional banks of the Register File. The WSP1600 DSP core also features an extra set of I, M, L registers for the Data Address Generators as well as powerful MIN & MAX instructions. Similar to the PM, the DM in the WSP1600 core is implemented with Synchronous Dual-Access capability to allow both instruction and DMA triggered access to take place in the same cycle. 

The control needed for the enhance features and functions is achieved by standard ADSP-218X instructions and thus requiring no changes to the standard ADSP-218X compiler, assembler, or development environment. 

工艺：
代工厂：
应用：Audio, Voice, Speech, Sound Effects, Multi-media, Communication, etc.
特色：

FULLY compatible to ADSP-218X
    All standard ADSP-218X application codes run on it.
FULLY synchronous and synthesizable design
    ASIC as well as FPGA implementations are straight-forward and proven.
Optimized for easy embedding in SOC designs
    All I/Os are expanded (not multiplexed).
    PM and DM sized are easily configured (changed) and optimized for target applications.
Enhanced for more efficient coding and lower power operations
    For the same application, WSP1600 code is expected to be smaller than the ADSP-218X code.
Most optimized Mult/MAC design 
    Small, fast, and all Mult/MAC instructions complete in one cycle.
High-Speed non-pipelined design
    Purely scalar design (1MHz = 1MIPS), ideal for real-time applications.
    All instructions complete in one clock cycle with NO exceptions.
    Very small gate count.