IP核名称：General purpose, high performance customizable fixed-point DSP core

简要描述：The CDSPtm is a general purpose, high performance customizable fixed-point DSP core featuring high execution speeds for both signal-processing algorithms and standard microprocessor applications. It is meant to be used as an embedded cell in ASIC's developed on most of the current 0.6u and below technologies. It is highly customizable and can be targeted at a large number of technologies thanks to its parameterized, HDL-only based design. The CDC-XP can be optimized for most of the common DSP algorithms to obtain a highly efficient, low power and small area implementation. It is therefore most suitable for low-cost, high-volume applications.

特色： Single-cycle execution for most instructions.

  Two-operand instruction set with one operand residing in memory and the other in a register

  A dual-operation instruction-word option enabling sustained rates of two operations per cycle in memory-access intensive algorithms such as buffered image processing and adaptive filtering

  Four internal data busses enabling up to four internal data transfers per cycle

  Zero-cycle Block-repeat capability plus a standard looping instruction

  Special bank-based memory architecture enabling efficient usage of data types that are smaller than a processor word

  Very compact code and large addressing space

  Eight logical shifts and four arithmetic shifts

  Configurable hardware multiplier

  Provision for full accommodation of MAC(s) by mapping one MAC input and the output on the register file and providing the full range of indexed addressing modes for the second input

  Configurable butterfly unit enabling execution speeds comparable with the cutting edge parallel DSP processors on the market.

  Up to three index registers fully featured with modulo and bit-reversed post-increment addressing capability

  A constant-memory table-lookup pointer featured with post-increment/post-decrement options

  Synchronous program memory implementable as a RAM/ROM combination, enabling the DSP with run-time programmability feature via the comm ports

  Less than one cycle response when in wait mode allowing fast synchronization with predictable asynchronous events

  Option for shadow registers allowing zero-cycle context saving for one or more levels of interrupts