The AU-J1100 Java Bilingual Processor Core is a Java plus legacy code processor core targeted
at efficient high performance Java execution. It directly executes both Java code and popular,
industry standard legacy code based on the RISC instruction set that originated at Stanford*, thus
providing software compatibility for existing applications, as well as fast, efficient Java
execution. New applications can be written in Java or traditional languages, and compiled into
either Java bytecodes or legacy binaries, as is best suited for the situation. With a CaffeineMarks
overall score of 20 CaffeineMarks/MHz, Java performance is significantly faster than other
software *and* hardware Java solutions. This is due to several proprietary mechanisms that
boost Java performance. In addition to fast Java execution, uncompromised legacy performance
is achieved with Aurora VLSI's proprietary architecture. Performance on legacy code is
comparable or better than that of other single scalar legacy processor cores at the same frequency
and price points. See the white papers at www.auroravlsi.com for a discussion of the software
advantages of this bilingual processor. The AU-J1100 Java Bilingual Processor Core is available
as a synthesizable Verilog model from Aurora VLSI, Inc.

Java Processor Core
• Hardware accelerated Java execution- 20 CaffeineMarks/MHz measured)
• Proprietary hardware accelerates common Java specific functions
• Execution of all “The Java Virtual Machine Specification” bytecodes
• Proprietary bytecode execution for the JVM run time system (system functions)
• 5 stage RISC pipelineLegacy Processor Core
• Smallest possible 32 bit processor core- 20K – 25K gates
• Low power- .15 - .3mW/MHz
• Popular, industry standard legacy instruction set based on the RISC instruction set
that originated at Stanford*
• Good performance- 160/280 Dhrystone 2.1 at 200/350MHz (predicted)
• Peak execution rate of 1 instruction/cycle (single scalar design)
• 5 stage RISC pipeline
• Coprocessor port used by the operating system, to manage the Java Core
Cache Unit
• Separate instruction and data cache
• Sizes are configurable from 256 bytes to 8Kbytes each
• Direct mapped
• 16 byte line sizes
• Writeback data cache
• Physically addressed, virtually indexed
• Byte parity
• Direct access to data and tags of each cache for cache management
• Separate instruction and data high bandwidth memory interfaces- 8 bytes/cycle peak
Memory Management Unit (MMU)
• Simultaneous instruction and data virtual address translation for high performance
• 4K byte page size
• Page based cacheability and write protection
• Global and process dependent virtual addresses