The AU-C02XX 32 Bit Tiny, Low Power SPARC Processor Cores are a family of small, low
power 32 bit SPARC processor cores targeted at embedded controller, wireless, and other
portable applications. For lowest power and smallest gate count, each processor of this family of
processor cores, includes the base processor and a combination of any of a) caches, b) MMU,
and/or c) floating point. The user selects the processor from this processor family that has only
user’s required functionality, and therefore does not waste area or power on unnecessary
functions. Power consumption is expected to be .3mW/MHz or less in .18u technologies. Power
levels in the .15mW/MHz range can be attained with cell libraries that support lower supply
voltages (1.2V). The AU-C02XX Processor Cores are available as synthesizable Verilog models
from Aurora VLSI, Inc.

Basic Processor Core
• Smallest possible 32 bit processor core
• 20K – 25K gates
• Low power- .15 - .3mW/MHz
• 32 bit SPARC instruction set
• Good performance- 160/280 Dhrystone 2.1 at 200/350MHz (predicted)
• Peak execution rate of 1 instruction/cycle (single scalar design)
• 5 stage RISC pipeline
• Coprocessor port for an optional user defined coprocessor
• Interrupt interface
Cache Unit
• Separate instruction and data cache
• Sizes are configurable from 256 bytes to 8Kbytes each
• Direct mapped
• 16 byte line sizes
• Writeback data cache
• Physically addressed (virtually indexed when MMU Unit is present)
• Byte parity
• Direct access to data and tags of each cache for cache management
• Separate instruction and data high bandwidth memory interfaces- 4 bytes/cycle peak
Memory Management Unit (MMU)
• SPARC reference MMU
• Simultaneous instruction and data virtual address translation for high performance
• 4K byte page size
• TLB
- 32 or 64 entries (configurable)
- Dual ported
- Hardware replacement upon TLB miss
Floating Point Unit (FPU)
• IEEE754-1985 floating point
• Fully compliant results for all floating point instructions computed in hardware
• Single and double precision
• Supports 32 bit and 64 bit floating point data loads and stores
• Floating point condition codes for floating point conditional branches