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Aurora VLSI, Inc.:AU-C01XX
类型:软IP
简短描述:32 Bit, Tiny, Low Power Processor Cores
详细描述:

The AU-C01XX 32 Bit Tiny, Low Power Processor Cores are a family of small, low power 32 bit
processor cores targeted at embedded controller, wireless, and other portable applications. For
lowest power and smallest gate count, each processor of this family of processor cores, includes
the base processor and a combination of any of a) caches, b) MMU, and/or c) floating point. The
user selects the processor from this processor family that has only user’s required functionality,
and therefore does not waste area or power on unnecessary functions. Power consumption is
expected to be .3mW/MHz or less in .18u technologies. Power levels in the .15mW/MHz range
can be attained with cell libraries that support lower supply voltages (1.2V). The AU-C01XX
Processor Cores execute popular, industry standard legacy code based on the RISC instruction set
that originated at Stanford*. The AU-C01XX Processor Cores are available as synthesizable
Verilog models from Aurora VLSI, Inc. Contact


工艺:
代工厂:
应用:
特色:

Basic Processor Core
• Smallest possible 32 bit processor core
• 20K – 25K gates
• Low power- .15 - .3mW/MHz
• Popular, industry standard legacy instruction set based on the RISC instruction set
that originated at Stanford*
• Good performance- 160/280 Dhrystone 2.1 at 200/350MHz (predicted)
• Peak execution rate of 1 instruction/cycle (single scalar design)
• 5 stage RISC pipeline
• Coprocessor port for an optional user defined coprocessor
• Interrupt interface
Cache Unit
• Separate instruction and data cache
• Sizes are configurable from 256 bytes to 8Kbytes each
• Direct mapped
• 16 byte line sizes
• Writeback data cache
• Physically addressed (virtually indexed when 32bLOW MMU Unit is present)
• Byte parity
• Direct access to data and tags of each cache for cache management
• Separate instruction and data high bandwidth memory interfaces- 4 bytes/cycle peak
Memory Management Unit (MMU)
• Simultaneous instruction and data virtual address translation for high performance
• 4K byte page size
• Page based cacheability and write protection
• Global and process dependent virtual addresses
Floating Point Unit (FPU)
• IEEE754-1985 floating point
• Fully compliant results for all floating point instructions computed in hardware
• Single and double precision
• Supports 32 bit and 64 bit floating point data loads and stores
• Floating point condition codes for floating point conditional branches

    SYNTILL8:M8051
    Aurora VLSI, Inc.:AU-C02XX
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