The M8051EW is a highly configurable softcore implementation of the industry standard 8051 microcontroller that features a two-clocks-per-machine cycle architecture. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC and FPGA SoC designs.

•   Binary and Memory cycle compatible with Intel 8051 Designs
  Fast 2-clocks per machine cycle implementation 
•   Richly featured hardware debugger: multiple breakpoints, instruction traceback, single step execution. Full debug access to all registers and memory spaces 
•   1Mbyte program and data address spaces 
•   Memory interfaces may be configured for synchronous or asynchronous devices 
•   External interfaces support wait states 
•   Optional demultiplexed program and data interfaces 
•   Up to 8 16-bit data pointers 
•   25-input, five level interrupt controller 
•   Full implementation of legacy peripherals: 32 GPIO ports, 3 16-bit counter timers and a full-duplex serial port. All legacy peripherals are optional 
•   Flexible interfacing options for external peripherals 
•   Power saving modes: powerdown, idle and run