类型:软IP
简短描述:M8051EW - Fast 8-bit Microcontroller with On-Chip Debug
详细描述:
The M8051EW offers a complete, high performance 8051 core and development kit, based around Mentor Graphics’s highly successful M8051W implementation of this popular 8-bit microcontroller. While the standard part is designed around a 12-clock machine cycle, both the M8051W and the M8051EW use a two-clock machine cycle to facilitate particularly fast and/or low power embedded solutions whilst retaining functional compatibility with the industry standard part.
It also features support for both up to 1 Mbyte of Program memory and up to 1 Mbyte of external Data Memory. The IP is supported by many 3rd-party C compilers and assemblers. For example, Mentor Graphics uses the C51 compiler from Keil Software for internal development and testing.
The M8051EW also features a Debug Mode in which it can be driven in singlestep fashion through a dedicated Debug interface. This aspect of the M8051EW is intended for use with First Silicon Solutions (FS2)’s In-Target System Analyzer for the M8051EW to provide a range of debugging features from basic stop/start or single-step execution and breakpoint support to reconstruction of execution history and capture of data memory, program memory and SFR accesses.
工艺:
代工厂:
应用:
特色:
• Two clocks per machine cycle architecture
• JTAG Interface and software for debug
• Up to 1 Mbyte of external Data Memory, accessible by a choice of interfaces
• Up to 256 bytes of Internal Data Memory
• Up to 1 Mbyte of RAM or ROM Program Memory, accessible by a choice of interfaces
• Support for synchronous and asynchronous Program, External Data & Internal Data Memory
• Wait states support for slow Program and External Data Memory
• Software compatible with Intel 8051, 8031, 87C51 and 8052 equivalents
• 2 or 3 16-bit timer/counters (optional)
• Full-duplex serial port (optional)
• Intel-compatible I/O ports
• Max 25 source, 2 or 4-level interrupt controller; choice of handling scheme
• Option of 1, 2, 4 or 8 data pointers
• Support for user-defined SFRs
• Separate demultiplexed memory interface ports
• Fully synthesizable
• Scan test ready