The AU-NB8006 Ethernet 10/100 AMBA Subsystem provides an Ethernet 10/100 peripheral
subsystem for AMBA based SOCs. It contains an Ethernet 10/100 MAC that connects
seamlessly to the AMBA AHB Bus. A DMA Engine is included to move Ethernet frame data.
The figure below shows its use within an SOC. The Ethernet 10/100 AMBA Subsystem Core is
available as a synthesizable Verilog model from Aurora VLSI, Inc.

Ethernet 10/100 MAC
• 10mb/s or 100mb/s Ethernet line speeds
• IEEE 802.3 compatible, supports IEEE 802.3x and IEEE 802.3Q for flow control
• Industry standard MII or RMII interface to the PHY
• Optional two-part deferral implemented
• Full and half duplex
• Automatic retries after collision, programmable retry counter
• Automatic padding and removal of PAD bytes to meet minimum frame size
• FCS generation for transmitted packets, and checking on received packets
• MDIO interface for PHY management
• Programmable address filtering
• Frame status captured in 2 status FIFOs
- Transmit Status FIFO- 4 entries
- Receive Status FIFO- 4 entries
• 128 to 2048 byte Transmit FIFO
• 128 to 2048 byte Receive FIFO
DMA/Host Interface
• AMBA AHB Bus interface
• 2 channel DMA Engine
- transmit data DMA from data source to Transmit FIFO
- receive data DMA from Receive FIFO to data destination
• Physical DMA addresses
• Programmable DMA starting address
• Programmable DMA transfer count- up to 64 Kbytes
• Programmable DMA AMBA Bus interface transaction size- 8 to 1024 bytes
• Programmable DMA AMBA Bus data transfer size- 4 or 8 bytes
• Locked DMA operation optional (software programmable)
• Direct software writes or information extracted from descriptors in memory, to
program DMA control information
• Dedicated AMBA Bus master interface for each DMA channel
• AMBA Bus slave interface for register reads and writes
• Interrupts:
- transmit frame DMA completed
- receive frame DMA completed
- frame transmit completed
- frame receive completed