Mismatches in transistor threshold voltage, resistance, and capacitance are dominant factors in IC performance and wafer yield. Mismatch in Vt can increase offset voltage, CMRR and poor performance, differences in turn on current in digital circuits can produce timing errors, reduce design margins, and impact yield. The impact of mismatch becomes greater as dimension of the transistors becomes smaller.

 

Ridgetop’s PDKChek measures die-level process-induced variations, both random and systematic, in Vt, R, C, Ion parameters. It is an unobtrusive, standalone IP block designed to accurately and precisely measure the variation in parameters resulting from the randomness inherent to processing in manufacturing.

Benefits:

(1)     Independent verification of process design kit (PDK) parameters

(2)    Expedite problem solving

(3)   Faster time-to-market by reducing the number of design iterations needed

(4)   Improve yield by optimizing design margin