The MAC-PCI IP core is a combination of the Ethernet Media Access Controller (MAC) HDL core - and the 32-bit 33 MHz Master/Slave PCI Host Interface core (PCI-M32). The core is intended to simplify the Ethernet networking support development in PCI based systems and applications.

A variety of available PHY interfaces facilitates the controller’s integration with a wide range of third-party transceivers. While the implementation of the most common PCI Local Bus interface guarantees seamless integration with a large number of PCI-equipped hardware devices, an available Linux driver allows users to skip basic software development stages and concentrate on designing the main application. Both the integrated scatter/gather DMA Controller and extended filtering features decrease CPU overhead, whereas advanced interrupt mitigation lowers the number of necessary interrupt support routines. Configurable internal FIFO’s architecture and low power capabilities make MAC-PCI a perfect solution for both resource and power limited applications.

The MAC-PCI is a design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states, and a synchronous reset; therefore, scan insertion is straightforward.

• Descriptor "ring" or "chain" structures
• Single descriptor can point to two data buffers
• Auto descriptor list pooling

cast_mac-pci.rar