类型:Soft IP
简短描述:SoC Kernel for ARC with AMBA Bus Systems
详细描述:
The SOCK-ARC provides the essential IP cores and infrastructure software needed for systems using a microprocessor from the ARC 600 or 700 families with the AMBA bus, a de facto open standard. Ready for software development out of the box but also easy to customize and extend, it serves as a basic platform for the rapid development of a variety of system-on-chip (SOC) applications.
The platform is well suited to a variety of AMBA-based SoC designs. It includes the multi-master and arbitration features of the high-performance AHB bus, and a bridge to the slower APB peripherals bus. The architecture makes it straightforward to add additional IP cores or custom logic to either bus.
The platform includes synthesizable HDL cores for the AHB and APB buses, plus various timers, controllers, interface functions, communications functions, and an internal SRAM block. (FPGA netlist versions are also available.) The individual cores are also available separately.
Generous standard deliverables include Software device drivers, boot code, service routines, and support for an embedded real-time operating system (RTOS). The included SOC test and validation suite features an AMBA Bus Functional Model.
工艺:
代工厂:
应用:Provides a system development head start for a wide range of applications, from low-power, portable, or inexpensive 600-based products through more sophisticated, high-performance products using a 700 family processor.
特色:
Integrated IP cores and software subsystem provides basic infrastructure for many SoC applications
Platform saves significant time over acquiring and integrating separate element
Works with 32-bit ARC 600 or 700 family processors
Built on AMBA standard bus for broad applicability
Enables both the high-performance AHB and the APB peripherals buses
Easily add custom logic or additional IP cores to tailor or expand the system
Immediately begin software development and test
Supports ARC MetaWare® and other development tools
Complete infrastructure includes essential hardware and software
Included IP cores (also available separately)
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Microprocessor interface
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APB Bridge
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Timers
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Scalable Interrupt Controller
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Parallel I/O
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Internal SRAM with Controller
Software
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boot code
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Interrupt Service (ISR) code
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Main code with Scheduler
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Device driver code
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Hardware Level API
Plug-in architecture for user-defined custom IP blocks
Support for real-time operating systems (RTOS)
pip7-tdmi.rar