类型:软IP 简短描述:PLB RAPIDIO LVDS Design 详细描述:The Xilinx PLB RapidIO™ LVDS Intellectual Property (IP) solution is a LOGICCORE™ module that provides an interface between the IBM ® CoreConnect™ Processor Local Bus (PLB) and an LVDS based RapidIO interface standard. The PLB RapidIO LVDS design provides an interface between the PPC405 (via PLB CoreConnect Bus) and a RapidIO protocol network. The physical interface to the RapidIO bus uses the 8 bit LVDS standard. 工艺:0.25um 代工厂: 应用: 特色: