Xilinx:PLB DDR SDRAM Controller-广州星海集成电路基地有限公司官方网站

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Xilinx:PLB DDR SDRAM Controller

类型：软IP
简短描述：PLB DDR SDRAM Controller
详细描述：The PLB DDR SDRAM controller soft IP core connects to the PLB bus and provides the control interface for DDR SDRAMs. Other features include performing device initialization sequence upon power-up and reset conditions, auto-refresh cycles. It also supports single-beat and burst transactions, target-word first cache-line transactions, cacheline latencies of 2 or 3 set by a design parameter, and various DDR data widths set by a design parameter. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.
工艺：0.25um
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Xilinx:PLB Bus Structure

Xilinx:PLB EMC (DO-EDK)

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