类型：软IP
简短描述：8b/10b Decoder
详细描述：The 8b/10b Decoder IP core provides the decoding of 10-bit symbols into 8-bit bytes and an accompanying "K" bit. The core also provides the decoding of 268 unique transmitted characters: 256 byte values and 12 special ("K") characters. The core has fully synchronous operation. It tracks "running disparity" to verify that the disparity sequence of the received symbol is valid. The user has the choice of a LUT-based implementation, using FPGA slices, or a block memory-based implementation, using one of the dedicated on-chip block memory blocks. The core has multiple optional inputs and outputs, enabling the user to track data moving through the core. The block RAM implementation can be used to create a secondary ("B") Decoder with almost no additional resource overhead.
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