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Xilinx:LD-based Parallel Latch
类型:软IP
简短描述:LD-based Parallel Latch
详细描述:The LD-based Parallel Latch IP core is a latch-based data register with 1 to 64 bits width. Options provided are Clock Enable; Asynchronous Set, Clear and Init; and Synchronous Set, Clear and Init. It can optionally generate output as a Relationally Placed Macro (RPM) or as unplaced logic. Output in RPM form is columnar.
工艺:0.25um
代工厂:
应用:
特色:

    Xilinx:FIFO Generator
    Xilinx:RAM-based Shift Register
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