类型:软IP
简短描述:FD-based Shift Register
详细描述:The FD-based Shift Register module provides user-definable, unidirectional or bidirectional, shift capability with parallel and/or serial inputs and outputs. An optional clock enables asynchronous and synchronous controls. Options include Clock Enable; Asynchronous Set, Clear and Init; and Synchronous Set, Clear and Init. This core can be optionally generated as a Relationally Placed Macro (RPM) or as unplaced logic.
工艺:0.25um
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