类型:软IP
简短描述:FD-based Parallel Register
详细描述:The FD-based Parallel Register is a flip-flop-based data register that features 1 to 64 bits width. Options provided are Clock Enable; Asynchronous Set, Clear and Init; and Synchronous Set, Clear and Init. It can optionally generate output as a Relationally Placed Macro (RPM) or as unplaced logic. Output in RPM form is columnar.
工艺:0.25um
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