类型：软IP
简短描述：Distributed Memory
详细描述：The Distributed Memory IP core creates memory structures using Select RAM. It can be used to create Read Only Memory (ROM, single-port Random Access Memory (RAM, and pseudo-dual port RAM. The core supports data widths of up to 1024 bits. It supports depths ranging from 16 to 65,536 words for VirtexTM-II FPGAs and ranging from 16 to 4096 words for the Virtex, Virtex-E and SpartanTM-II families. Options are available for simple registering of inputs and outputs in addition to variable pipelining capabilities. Optional asynchronous and synchronous resets are available for the output registers. The module also can be generated as a relationally placed macro (RPM) or as unplaced logic.
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