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Xilinx:Asynchronous FIFO
类型:软IP
简短描述:Asynchronous FIFO
详细描述:The Asynchronous FIFO module performs all the necessary read and write pointer management, and generates status flags and handshake signals for interfacing with user logic. The core supports data widths up to 256 bits and memory depths of up to 65,535 locations. Memory can be implemented in either SelectRAM™ or distributed RAM and the read and write ports have fully synchronous and independent clock domains.
工艺:0.25um
代工厂:
应用:
特色:

    Xilinx:Twos Complementer
    Xilinx:BUFT-based Multiplexer Slice
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