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Xilinx:Accumulator
类型：软IP
简短描述：Accumulator
详细描述：The Accumulator IP core generates adder-, subtractor-, and adder/subtractor-based accumulators operating on signed or unsigned input. Data is entered on Port B. An alternate option allows the value of Port B being set to a constant. Carry input and carry/borrow/overflow options are also available. The range of inputs is from 1 to 64 bits wide and outputs from 1 to 66 and the module supports user-programmable feedback scaling.
工艺：0.25um
代工厂：
应用：
特色：

    Xilinx:Viterbi Decoder, (IEEE 802-Compatible)
    Xilinx:Adder/Subtracter
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