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Xilinx:Digital Down Converter (DDC)
类型:软IP
简短描述:Digital Down Converter (DDC)
详细描述:The Digital Down Converter (DDC) IP core product is typically used in wireless and wireline communication systems to perform channel access functions in all-digital receivers. The core has a configurable datapath comprising a mixer, a DDS, an optional CIC filter, and a series cascade of two optional polyphase decimators. The CIC rate changes from 4 to 16383, with support for decimation rate adjustment in real-time. The DDC core has two polyphase decimation filters each with a configurable filter length from 0 to 1024 taps, and coefficient precision from 1 to 32 bits. Each of the polypahse decimators supports rate changes between 2 and 8, inclusive. The core has 0.02 Hz DDS tuning resolution and 25 to 108 dB DDS spurious free dynamic range. It has bias-free convergent rounding employed between datapath components to avoid DC bias issues. The core also has a microprocessor style interface to adjust the CIC decimation rate and tune the DDS.
工艺:0.25um
代工厂:
应用:
特色:

    Xilinx:Convolutional Encoder
    Xilinx:Digital Up Converter
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